This invention relates to a method of fabricating a semiconductor integrated circuit device, to a semiconductor integrated circuit device technique; and, in particular, to a method of fabricating a semiconductor integrated circuit device comprising an embedded interconnection having copper as the main conducting layer, and an effective technique applied to a semiconductor integrated circuit device.
In a technique for forming interconnections comprising semiconductor integrated circuit devices, semiconductor devices, electronic circuit devices and electronic devices, a conducting film, such as, for example, aluminum or tungsten, is deposited over an insulating film and is patterned by ordinary photolithography and dry etching.
However, in this interconnection forming technique, as devices and interconnections comprising semiconductor integrated circuit devices become finer, interconnection resistances are largely increasing, interconnection delays are occurring, and a limit is being reached to further performance improvements of the semiconductor integrated circuit devices.
In recent years, an interconnection forming technique known as the Damascene method has been developed. This Damascene method may be broadly distinguished into two types, i.e., the Single Damascene method and the Dual Damascene method.
In the Single Damascene method, after forming an interconnection slot in an insulating film, for example, a main conducting layer for forming interconnections is deposited over this insulating film and in the interconnection slot, and an embedded interconnection in the interconnection slot is formed by polishing this main conducting layer by, for example, CMP (Chemical Mechanical Polishing), so that it is left only in the interconnection slot.
In the Dual Damascene method, after forming a connecting hole to connect with the interconnection slot and a substrate interconnection in the insulating film, a main conducting layer for forming interconnections is deposited over this insulating film and in the interconnection slot and connecting hole, and an embedded interconnection in the interconnection slot and the connecting hole is formed by polishing this main conducting layer by, for example, CMP (Chemical Mechanical Polishing), so that it is left only in the interconnection slot and connecting hole.
In both methods, a material such as copper or the like is used as the material of the main conducting layer of the interconnections from the viewpoint of improving the performance of the semiconductor integrated circuit device. Copper has the advantage that, compared to aluminum, its resistance is lower and its permitted current for reliability is more than two orders of magnitude higher. Hence, the film can be made thinner to obtain the same interconnection resistance, and the capacitance between adjacent interconnections can be reduced.
However, compared to other metals, such as aluminum or tungsten, it diffuses easily in the insulating film if copper is used as the interconnection material, therefore, it is necessary to form a thin conducting barrier film to prevent diffusion of copper on the surface of the main conducting layer including copper (bottom surface and side surfaces), i.e., on the inner wall surfaces (side surfaces and bottom surface) of the interconnection slot. There is also a technique to prevent diffusion of copper in the embedded interconnection from the upper surface of the embedded interconnection into the insulating film by depositing a cap film including, for example, silicon nitride so as to cover the upper surface of the embedded interconnection over the entire surface on the upper surface of the insulating film in which the interconnection slot is formed.
This kind of embedded interconnection technique is mentioned in, for example, Japanese Unexamined Patent Publication No. Hei 10(1998)-154709, wherein the embedded properties of a fine contact hole with a high aspect ratio are improved by forming the embedded interconnection of high purity copper having an oxygen concentration or sulfur concentration not exceeding 3 ppm, thus enhancing the surface diffusion properties and fluidity of the copper.
In Japanese Unexamined Patent Publication No. Hei 11(1999)-87349, for example, a technique is disclosed wherein, after forming the interconnection slot and connecting hole in the insulating film, a copper film is formed by sputtering using a target having a purity of 99.999 wt % (5N) or higher. In this Publication, to facilitate embedding of the copper, a titanium nitride/titanium film is formed as a barrier layer over the surface of the interconnection slot and connecting hole.
In Japanese Unexamined Patent Publication No. Hei 11(1999)-87509 or Japanese Unexamined Patent Publication No. Hei 11(1999)-220023, for example, a technique is disclosed wherein the barrier layer on the bottom surface of a via is removed to lower the resistance of the via.
In Japanese Unexamined Patent Publication No. Hei 11(1999)-16912, for example, a technique is disclosed wherein the oxide layer formed in the interconnection part exposed at the bottom of the connecting hole is eliminated by applying heat, plasma or ultraviolet irradiation in a reducing atmosphere.
However, according to tests performed by the Inventors, the following problems were found in semiconductor integrated circuit device techniques comprising embedded interconnections having copper as the main conducting layer.
Firstly, as the dimensions of the embedded interconnections (line widths, thicknesses, distances between centers of adjacent interconnections and intervals between adjacent interconnections) having copper as the main conducting layer become finer, the cross-sectional surface area of the high resistance conducting barrier film become larger relative to the interconnection cross-sectional surface area, and the resistance of the embedded interconnection is increases. As a result, there is a limit to performance improvement of the semiconductor integrated circuit device even though copper is used to enhance performance.
Secondly, to resolve the first problem, if the barrier film is simply made thinner without performing any special treatment or is eliminated, the interconnection resistance can be reduced, but diffusion of copper occurs and the insulation breakdown resistance between mutually adjacent embedded interconnections falls considerably. As a result, a high reliability semiconductor integrated circuit device cannot be provided. Also, as the yield of the semiconductor integrated circuit device falls, the cost of the semiconductor integrated circuit device increases.
Thirdly, when a silicon nitride film is used as the cap film on the embedded interconnection having copper as the main conducting layer, a silicide substance is formed at the interface of the copper and silicon nitride film, and the resistance of this embedded interconnection increases. It was found for the first time by experiments carried out by the Inventors that diffusion of copper is a major reason for this, as will be described later. Consequently, there is a limit to improving the performance of the semiconductor integrated circuit device. There is also a problem in that the yield and reliability of the semiconductor integrated circuit device are seriously affected.
Fourthly, peeling occurs between the interconnection layer of the embedded interconnection and the insulating film (e.g., the aforesaid cap layer) formed over the upper layer. As a result, the yield and reliability of the semiconductor integrated circuit device is seriously reduced.
It is therefore an object of this invention to provide a technique for reducing the resistance of the embedded interconnection having copper as the main conducting layer.
It is another object of this invention to provide a technique for improving the insulation breakdown resistance between embedded interconnections having copper as the main conducting layer.
It is another object of this invention to provide a technique for improving adhesion between the interconnection layer and the cap film of embedded interconnections having copper as the main conducting layer.
It is another object of this invention to provide a technique for improving the reliability of an integrated circuit semiconductor device comprising embedded interconnections having copper as the main conducting layer.
It is another object of this invention to provide a technique for improving the yield of an integrated circuit semiconductor device comprising embedded interconnections having copper as the main conducting layer.
It is another object of this invention to provide a technique for improving the performance of an integrated circuit semiconductor device comprising embedded interconnections having copper as the main conducting layer.
The above and other objects and novel features of the invention will become clear from the following description and the drawings.
The following is a simple description in outline of the aspects and features of the present invention disclosed in this application.
This invention comprises an embedded interconnection having copper as a main component embedded in a depression formed in an insulating film via a conducting barrier film, and a cap insulating film formed so as to cover the upper surface of the insulating film and embedded interconnection layer, the concentration of components other than copper in the-embedded interconnection not exceeding 0.8 At. % in the finished semiconductor chip.
In accordance with a feature of this invention, as regards the side wall part of the aforesaid depression, the thickness of the thickest part or thinnest part of the conducting barrier film is less than 10 nm.
In accordance with another feature of this invention, as regards the side wall part of the aforesaid depression, the thickness of the thickest part or thinnest part of the conducting barrier film is not more than 2 nm.
In accordance with another feature of this invention, the conducting barrier film in the aforesaid depression does not exist.
In accordance with still another feature of this invention, an embedded metal interconnection layer is in direct contact in the aforesaid depression.
This invention comprises a method including a step of forming a depression in an insulating film formed over a semiconductor substrate, a step of depositing a conducting barrier film over the insulating film including the interior of the depression, a step of depositing a metal film having copper as the main component over the conducting barrier film including the interior of the depression, and a step of forming an embedded metal interconnection layer via the conducting barrier film in the interior of the depression by removing the metal film and conducting barrier film, the concentration of components apart from copper in the embedded metal interconnection layer when the semiconductor chip formed from the aforesaid semiconductor substrate is finished, not exceeding 0.8 At. %, and the purity of the copper in the metal film when the metal film having copper as the principal component is formed, being at least 99.999%.
In the aforesaid method of this invention, the aforesaid metal film is formed by a sputtering technique using a target including copper of at least 99.999% purity.
This method of the present invention, comprises a step wherein, after removing the aforesaid metal film by chemical mechanical polishing to form the embedded interconnection, the upper surface of the insulating film and indebted interconnection layer is plasma treated in a gas atmosphere having reducing properties, and a step wherein a cap insulating film is formed over the insulating film and embedded metal interconnection layer after plasma treatment.
In the method of this invention, the gas atmosphere having reducing properties has hydrogen as its main component.
In this method, the gas atmosphere having reducing properties also has a nitriding action.
In this method, the gas atmosphere having reducing provinces contains ammonia as its main component
In this method, the step of forming the embedded metal interconnection layer by removing the metal film is performed by abrasive particle-free chemical mechanical polishing.
In this method, the concentration of components apart from copper does not exceed 0.02 At. %.
In this method, the thickness of the thickest part or thinnest part of the conducting barrier film in the side wall of the aforesaid depression is less than 10 nm.
In this method, the thickness of the thickest part or thinnest part of the conducting barrier film in the side wall of the aforesaid depression is not more than 2 nm.
This method further comprises a step wherein, after forming the aforesaid depression, and prior to the step of depositing the conducting barrier film, the semiconductor substrate is plasma treated in a gas atmosphere having reducing properties.
The method of this invention comprises a step of forming a depression in an insulating film formed over a semiconductor substrate, a step of depositing a metal film having copper as the main component over the insulating film including the interior of the depression without the intervention of a conducting barrier film, and a step of forming an embedded metal interconnection layer in the interior of the depression without the intervention of a conducting barrier film by removing the metal film, the concentration of components apart from copper in the embedded metal interconnection layer, when the semiconductor chip formed from the aforesaid semiconductor substrate is finished, not exceeding 0.8 At. %, and the purity of the copper in the metal film, when the metal film having copper as the principal component is formed, being at least 99.999%.
The method of this invention comprises a Damascene interconnection forming step, comprising a step of forming a depression in an insulating film formed over a semiconductor substrate, a step of depositing a conducting barrier film over the insulating film including the interior of the depression, a step of depositing a metal film having copper as the main component over the conducting barrier film including the interior of the depression, a step of forming an embedded metal interconnection layer via the conducting barrier film in the interior of the depression by removing the metal film and conducting barrier film, and a step of forming a cap insulating film over the insulating film and embedded metal interconnection layer, the concentration of components apart from copper in the embedded metal interconnection layer, when the semiconductor chip formed from the aforesaid semiconductor substrate is finished, not exceeding 0.8 At. %, and the purity of the copper in the metal film, when the metal film having copper as the principal component is formed, being at least 99.999%.
The method of this invention comprises a Dual Damascene interconnection forming step, comprising a step of forming an embedded interconnection slot and connecting hole in an insulating film formed over a semiconductor substrate, a step of depositing a conducting barrier film over the insulating film including the embedded interconnection slot and connecting hole, a step of depositing a metal film having copper as the main component over the conducting barrier film including the embedded interconnection slot and connecting hole, a step of forming an embedded metal interconnection layer via the conducting barrier film in the embedded interconnection slot and connecting hole by removing the metal film and conducting barrier film, and a step of forming a cap insulating film over the insulating film and embedded metal interconnection layer, the concentration of components apart from copper in the embedded metal interconnection layer, when the semiconductor chip formed from the aforesaid semiconductor substrate is finished, not exceeding 0.8 At. %, and the purity of the copper in the metal film, when the metal film having copper as the principal component is formed, being at least 99.9990%.
The method of this invention comprises a step wherein, after forming the embedded interconnection slot and connecting hole, the aforesaid semiconductor substrate is plasma treated in a gas atmosphere having reducing properties prior to a step of depositing the conducting barrier film.
The method of this invention comprises a step wherein, after a step of forming the embedded interconnection layer by removing the metal film by chemical mechanical polishing, the upper surface of the insulating film and embedded interconnection layer is plasma treated in a gas atmosphere having reducing properties prior to the step of forming the cap insulating film.